The multiplying DAC is an ideal building block for waveform generation applications. Because the R-2R architecture of the multiplying digital-to-analog converter (DAC) is ideal for low-noise, low-glitch, fast-settling applications.
When generating waveforms from a fixed reference input voltage, important communication specifications must be considered, including settling time, intermediate level glitch, and digital SFDR.
Today we will analyze these important DAC specifications related to waveform generation.
Setup time
Assuming the DAC is driven by a real wideband low-impedance source (reference voltage and ground pin), it is set up quickly. Therefore, the slew rate and settling time of the multiplying DAC are primarily determined by the op amp. Specifications that determine the operational performance of an op amp include its input capacitance (which must be kept to a minimum) and a 3 dB small signal bandwidth. Note that the op amp's bandwidth is limited because it must drive the larger load of the DAC feedback resistor. For example, a 10 kΩ feedback resistor is a fairly large load that is the primary pole in determining the bandwidth of the circuit configuration.
Intermediate level glitch
For the R-2R structure, the main glitch caused by the code change occurs when a 1 LSB change occurs around the intermediate level. In a 12-bit system (such as the DAC AD5444), the intermediate level change is a code change from 7FFH to 800H or from 800H to 7FFH. If the burr is severe, it may adversely affect the motor/valve/actuator control application. When the multiplying DAC attempts to change from 7FFH to 800H, the MSB switching speed of the DAC is lower than the switching speed of the other bits. Therefore, within a few nanoseconds before the MSB switches to 1, the DAC sees 000H. This is the case with the yellow curve in Figure 2; the output changes towards 0 V before the MSB switches and pulls the DAC output back to 800H.
Figure 2. Intermediate level glitch
Digital SFDR
Spurious-Free Dynamic Range (SFDR) refers to the available dynamic range of the DAC beyond which spurious noise can interfere with or distort the fundamental signal. SFDR measures the difference between the amplitude of the fundamental and non-harmonic-related spurs within the range of the fundamental to DC-to-Nyquist bandwidth (half the DAC sampling rate). Narrowband SFDR measures SFDR in any window range. There are countless points in each cycle of an ideal sine wave. However, digitally generated sine waves are limited by the fixed update rate and DAC resolution. The number of points per cycle is given by:
among them:
N = number of sampling points
Clock = DAC update rate
fOUT = output frequency of the generated waveform
Figure 3 shows a 20 kHz sine wave with an update rate of 1 MHz using a 12-bit AD5444 with 50 samples per cycle. The AD5444 has a maximum update rate of 2.7 MSPS. To generate more waveforms at the sample point, a faster update rate must be used. The parallel interface AD5445 provides a maximum update rate of 20 MSPS.
Figure 3. Wideband SFDR, fOUT = 20 kHz, clock = 1 MHz
Laptop Stand Holder Adjustable,Laptop Stand Holder Desk,Laptop Stand Holder Ergonomic,Laptop Stand Holder Ergonomic Adjustable,etc.
Shenzhen Chengrong Technology Co.ltd is a high-quality enterprise specializing in metal stamping and CNC production for 12 years. The company mainly aims at the R&D, production and sales of Notebook Laptop Stands and Mobile Phone Stands. From the mold design and processing to machining and product surface oxidation, spraying treatment etc ,integration can fully meet the various processing needs of customers. Have a complete and scientific quality management system, strength and product quality are recognized and trusted by the industry, to meet changing economic and social needs .
Laptop Stand Holder Adjustable,Laptop Stand Holder Desk,Laptop Stand Holder Ergonomic,Laptop Stand Holder Ergonomic Adjustable
Shenzhen ChengRong Technology Co.,Ltd. , https://www.dglaptopstandsupplier.com